The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to leakage power estimation in an integrated circuit (IC) device.
Power consumption, both dynamic and leakage, is one of the major concerns in IC design. In particular, sub-threshold leakage (or leakage power) may be growing with each successive design generation. For example, as supply voltage is lowered (e.g., to reduce dynamic power consumption), threshold voltage may also be lowered (e.g., to maintain low gate delay or high frequency). However, lowering the threshold voltage may affect leakage power nonlinearly.
In some implementations, leakage power may be assumed to have a constant value during run-time. However, leakage power may vary during run-time, for example, due to changes in temperature, supply voltage, or threshold voltage. Accordingly, power management techniques may be less accurate without knowledge of leakage power.